1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to multiport semiconductor memory devices.
2. Related Art
Along with recent advancements of semiconductor technologies, smaller-size and larger-capacity memories that allow high-speed reading/writing operations have been developed. Further, a so-called multiport memory including plural input ports and output ports has been used for reading/writing data of different addresses.
Coupling capacitance between bit lines in memory devices can be sufficiently large to interfere with memory operations. Where the coupling capacitance is sufficiently large, data sense operations must be delayed until enough bit line difference occurs for a read operation. Without any compensation for coupling capacitance, performance of the memory device can be degraded. For most memory devices, each bit line has a coupling effect on an adjacent bit line voltage swing. The coupling effect will cause the memory device to malfunction, or will reduce the performance of the device. Twisted bit line techniques have been applied to single port memories. Even when the bit lines are twisted as in single port memory, read and write data still have coupling capacitance issues because the twisting is imperfect compensation. In multiport memories with concurrent Read and Write bit lines coupling to adjacent Read bit lines is most significant. The coupling interactions are more complex than in single port memories. Therefore, a need exists to compensate for bit line coupling capacitance in multiport memory devices.